Manufacturing and production of integrated circuits is a multi-billion dollar industry. A substantial amount of resources are utilized in connection with improving performance of integrated circuits, increasing yield, and increasing density of integrated circuits. For example, aggressive scaling (miniaturization) of devices has resulted in interconnect lines that are denser and shorter in width than ever before. As signals are delivered through interconnect lines, parasitic capacitance between the interconnect lines can become problematic due to cross talk and wire delays that are associated with such capacitance and resistance. If parasitic capacitance and resistance are not properly characterized and understood, cross talk and wire delays can compromise integrity and performance of the circuit. Accordingly, it is imperative that characteristics of interconnect parasitic capacitances be understood, measured, modeled, and controlled. Moreover, it is important to characterize all interconnect parasitic capacitances and resistances within a VLSI circuit in order to determine whether or not such elements fall outside bounds of design specifications and to characterize VLSI technology.
While there have been monumental advances related to increasing density of VLSI circuits, systems and/or methods of characterizing interconnects within VLSI circuits have not experienced such advances. For example, while interconnect capacitance exists (and thus can theoretically be measured) during fabrication of VLSI circuits, conventional systems and/or methodologies only measure interconnect capacitance after fabrication of a VLSI circuit has been completed. Characterization is then performed via directly contacting probes with large pads (80–100 μm) connected to the interconnects. The pads have to be large enough to enable positioning of a probe with an optical microscope. Moreover, conventional systems and/or methodologies require expensive, complicated, and sizeable testing structures to obtain measurements relating to capacitance of interconnects within VLSI circuits. Such conventional systems and/or methodologies are further associated with various other shortcomings, such as an inability to obtain in-line capacitance measurements due to a requirement for large pad area. Furthermore, contacting interconnects with probes can damage interconnect surfaces, thus compromising operability of VLSI circuits.
Scanning probe microscopy was developed to alleviate some of the aforementioned deficiencies by reducing size of a probe required to contact interconnect surfaces for both imaging and measuring parameters of the interconnects being tested. A direct contact measurement of small capacitances related to interconnects, however, is problematic as capacitance of cantilevers attached to probes are similar in magnitude or larger than parasitic interconnect capacitances desirably measured. Furthermore, oxide resident upon interconnect surfaces and tips of cantilevers can reduce accuracy of capacitance measurements.
In view of at least the above, there exists a strong need in the art for a system and/or methodology facilitating improved characterization of VLSI interconnect capacitance.